Verilog Tutorial and list of other Tutorials

From VerilogWiki

Verilog Primer

This is a wiki based tutorial that you can edit and and add topics to.

Chapter 1: Introduction to Verilog hardware description language

Chapter 2: Verilog Structure

• 2.1 Modules
• 2.2 Structural Design with Gate Primitives and the Delay operator
• 2.3 Structural Design with Assignment Statements
• 2.4 Structural Design with using Modules
• 2.5 Behavioral Design with Initial and Always blocks

Chapter 3: Verilog Syntax Details

• 3.1 Structural Data Types: wire and reg
• 3.2 Behavioral Data Types: integer, real, and time
• 3.3 Number Syntax
• 3.4 Behavioral Design with blocking and non-blocking statements
• 3.5 Arrays, Vectors, and Memories
• 3.6 Operators

Chapter 4: Verilog Design Flow

• Step 1: Create RTL Design Models and Behavioral Test Bench Code
• Step 2: Functionally Simulate your Register-Transfer-Level Design
• Step 3: Convert RTL-level files to a Gate-level model with a Synthesizer
• Step 4: Perform Gate Level simulations with FPGA or ASIC libraries
• Optional Step: Gate-level simulation with SDF timing information

Verilog Tutorials on other sites (not editable)

This is meant to be a list of papers that introduce the Verilog language to someone new to the language. Papers that are more about solving difficult design problems using Verilog should be put on the Verilog Books and Papers page. Also students and newbies may want to check out the Verilog Quick Reference Guides and Sites page for guides that can be printed.

• Verilog Tutorial the web site that donated the orginal text for the above Wiki Verilog Tutorial
• Verilog according to Tom by Prof. DeMicheli
• The Verilog Language - A Learner's subset by DJ Greaves
• Verilog Tutorial by Harsha Perla on www.electrosofts.com
• SystemVerilog Tutorial by Abhiram Rao on www.electrosofts.com
• Introduction to Verilog by Peter M. Nyasulu
• Verilog Tutorial by Deepak Kumar Tala on www.Asic-world.com
• Verilog HDL Quick Reference Guide By Stuart Sutherland
• Verilog Tutorial by John Sanguinetti (requires registration)
• The Designer's Guide to Verilog by Doulos
• Verilog Tutorial from Aldec (tool specific)
• Verilog Tutorial from the University of Texas at Dallas also has a quick tutorial embedded into it
• Verilog Tutorial Edited for CS141 by Lukasz Strozek at Harvard
• Verilog Manual written by Saleem Chauhan and maintained by Gerard M Blair at the University of Edinburgh, Scotland, UK
• Verilog Tutorial by Joshua Cantrell at UCLA
• Digital System Design a short Verilog Overview by Amir Masoud Gharehbaghi at Sharif University of Technology
• A Behavioral Design Approach in Verilog Hardware Description Language covers modeling a RAM using Verilog by Iuliana Chiuchisan and Alin Dan Protorac at University of Suceava
• Structural Modeling with Verilog a basic lecture from California State University, Long Beach
• Verilog for Computer Design a basic introduction lecture by Andy Phelps at University of Pennsylvania
• Verilog Gate Level Design a PDF of a PPT from Professor C.H. Chao at NTU
• Verilog-accelerating digital design by Gerard Blair at The University of Edinburgh